1. Field of the Invention
The present invention relates to an automatic decoding system for addressing a memory on a motherboard of an electronic processor of the PC Personal Computer type.
More particularly, but not exclusively, the invention relates to the hardware implementation of the automatic decoding for addressing in a PC motherboard in the available memory area of a flash memory equipped with at least an interface with LPC (Low Pin Count) serial protocol.
The present invention also relates to an electronic memory device monolithically integrated on a semiconductor and equipped with a pseudo-parallel interface.
More particularly, but not exclusively, the invention relates to a Flash memory for standard applications integrated with a LPC (Low Pin Count) interface block, used during normal operation applications, and with a parallel interface block, used almost exclusively during the testing step.
2. Description of the Related Art
The integrated electronic device to which the memory invention applies is a Flash memory for PC Intel-like motherboard applications and it has externally eleven address pins, eight data pins and some control pins among which the synchronism or clock signal CLK and a setting signal of the two interfaces IC.
The memory device of the invention is equipped with two communication interfaces: the one parallel or pseudo-parallel, A/Amux interface, and the other serial, LPC interface.
The first is intended to perform fast preprogramming operations before mounting the memory on the motherboard or during the device-testing step with automated testing equipment (ATE). The second is used during the normal personal computer operation.
There is a selection signal, called IC, allowing to pass from an operation interface to the other.
At present, the software for testing flows both at the EWS level (Testing on wafer) and at the Final Test level (Testing on assembled device) has been conceived for a parallel-mode operation. Substantially, in the testing step all considered addresses and data are supplied in the parallel mode, while only the clock signal CLK and other four pins are necessary for the serial communication protocol.
As it is well known in this specific technical field, the reading operation of a memory location of the cell matrix implies first of all the address of the location itself to pass.
The here-attached FIG. 1 schematically shows the structure of a motherboard of an electronic processor 1 of the PC type. As it can be seen in FIG. 1, blocks 2 and 3, called I/O Controller and Memory Controller, are intended to put a motherboard processor 10 and the system peripherals 6, 7 into communication with a memory 5 wherein the device operating system BIOS is stored; this occurs for each type of operation.
The other system blocks 8, 9 are those allowing the processor 1 to interface the external world and they are underlined in this case for descriptive purposes only.
Further four pins called ID<3:0> are available, among the others, in the integrated memory circuit, through which it is possible to address several memories in the same system in the LPC mode. The block intended to manage the addressing in the available memory area is the Memory Controller 3.
The selection process of a predetermined memory among several memories available in the system is now described in greater detail.
Each memory has four ID pins. With four available bits it is possible to have up to 2^4=16 different combinations.
This means that, by setting the highest addressable memory area at 64-Mbit, it is possible to address up to sixteen four-Mbit memories or eight eight-Mbit memories. Moreover, in the highest addressing area, it is possible to have memories simultaneously having the same or different size, respecting the available addressing area.
As it can be seen in the matrix scheme of FIG. 2, by addressing eight-Mbit memories and four-Mbit memories respectively, different patterns can be obtained. In fact an eight-Mbit memory can be followed by eight-Mbit memories or by two four-Mbit memories, but if the first addressable memory is a four-Mbit memory, four-Mbit memories can follow, for overall 8 Mbits, and only after 8-Mbit memories since the area windows addressable by the controller 3 can be either four-Mbit or eight-Mbit and higher-capacity devices (eight Mbits in this case) delimit the highest addressable window.
In summary, in other words, if the first addressable memory is a four-Mbit memory, only a four-Mbit memory can follow for 8 Mbits at the most.
Therefore, the second column of FIG. 2 shows an impossible case in reality.
The controller 3 function is to select the memory to be addressed. This controller 3 comprises a BIOS selection register comprising the information required for mapping memories correctly.
Memories are mapped in the addressing area through the addressing ID pins.
Supposing that the first memory, i.e., the one with ID<3:0>=0000, is to be mapped at the top of the addressing area, the following memories have ID<3:0>=0001, 0010 and soon increasing by one bit the address of the memory to be mapped with respect to the already mapped memory.
Assuming the above, in order to map several memories in the same system, ID pins of each memory are located at the hardware level in a corresponding. logic address. The LPC communication protocol helps at this point to understand which memory the controller 3 wants to talk to. In fact, as it can be seen in FIG. 3, after the protocol starting step and the “cycletype” step, specifying which reading or writing operation is to be performed, eight clock cycles occur in which the memory is polled to pass the memory location address on which the operation is to be performed. It is worth noting that, when performing the LPC protocol, information is always exchanged through a four-bit bus. Since, to address a location of an eight-Mbit memory, twenty bits are necessary and eight clock cycles are available in the LPC protocol in correspondence of which it is possible to pass 32 bits, not all passed bits are necessary for the addressing.
It is therefore possible to select four of these 32 bits to be used for comparison with ID pins and to know from the bit-to-bit correspondence which memory is polled, i.e., addressed, to perform the above-mentioned operation. It is possible to use, for example, the bits A<31:25> for the mapping and the bits A<24:21> for the comparison with ID pins. In case of matching between these bits it is worth continuing with the remaining protocol to complete the operation required.
It is usually assumed that the first memory to be addressed is put at the top of the addressable area and that ID pins are then increased and the logic addresses decreased.
The matching between address bits and ID pins in a Top_Down addressing can be seen for example in the following table:
TABLE 1MemoryNumberID3ID2ID1ID0A24A23A22A21 1(Boot)00001111 200011110 300101101 400111100 501001011 601011010 701101001 801111000 9100001111010010110111010010112101101001311000011141101001015111000011611110000
In order to address the memory being at the top of the addressable area it is conventionally necessary to pass through the address bits A<24:21> the value 1111 while for the following memory the value 1110 and so on. The following memory, as such, must have, for ID pins, a value being increased by one with respect to the pin ID value of the previous memory, but, since a top toward bottom addressing is performed, the logic address must decrease.
This implies that a logic is provided in the memory, which allows the comparison among ID pins and address bits.
If the first memory is to be put in correspondence with the least significant bit according to an opposed bottom-up convention, this logic should be modified to allow a one-to-one comparison between ID pins and address bits, i.e., to address the lowest memory (with ID<3:0>=0000) the value 0000 instead of 1111 should be given to the address bits A<24:21>.
Therefore, if the first memory is to be mapped at the most significant bit or at the least significant bit, i.e., at the top or bottom of the addressable memory area, a different decoding must be provided in the two cases.
The present invention is grafted on this technical problem to provide an innovative automatic decoding mode for mapping a non volatile memory device, particularly of the Flash type, having a LPC (Low Pin Count) serial communication interface and in the motherboard available addressing area.